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A 16-bit 2-cycle RISC-V-inspired CPU in the same footprint as a 65c02. For the SKY130 process Tiny Tapeout.

9 starsPython

RISCY-V02: A 16-bit 2-cycle RISC-V-ish CPU in the 6502 footprint

Name: RISCY-V02: A 16-bit 2-cycle RISC-V-ish CPU in the 6502 footprint
Availability: InStock
Author: mysterymath

by mysterymath·Mar 6, 2026·7 points·4 comments

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AI Analysis

●●●●GemWizardryZero to OneBig Brain

Proves RISC beats 6502 in 1970s constraints with 1.0-2.6x speedup, same transistor count.

Strengths

•2-stage pipeline with speculative fetch outperforms microcode PLAs in fixed 1MHz DRAM context.
•Thorough ISA documentation with cycle-by-cycle timing, interrupt handling, and code comparisons.
•Actual silicon layout submitted to Tiny Tapeout; not theory—demonstrates real architectural tradeoffs.

Weaknesses

•Niche audience: only matters if you care about retrocomputing or CPU design fundamentals.
•No working system software yet; value depends on community building around the ISA.

Post Description

Finally finished my little CPU project, RISCY-V02. I built it (with Claude) to challenge the notion that the 6502 was a "local optimum" in its transistor budget. Given the constraints of 1970s home computers (~1 MHz DRAM, so raw clock speed doesn't help), could RISC have been a better design choice? This design argues yes: pipelining, barrel shifters, and more registers beat microcode PLAs, questionable addressing modes, and hardware BCD.

Highlights:

8x 16-bit general-purpose registers (vs 3x 8-bit on 6502) 2-stage pipeline (Fetch/Execute) with speculative fetch 61 fixed 16-bit instructions 2-cycle interrupt entry (vs 7 on 6502) 13,844 SRAM-adjusted transistors (vs 13,176 for 6502 on same process) 1.0-2.6x faster than 6502 across common routines

GDS viewer: https://mysterymath.github.io/riscyv02-sky Tiny Tapeout Shuttle Entry: https://app.tinytapeout.com/projects/3829